1. Field of the Invention
The present invention generally relates to a method of connecting a device to a support, and relates to a terminal pad, or pad, for such a connection, and relates in particular to a method of connecting and to a pad for connecting which enable a flexible interconnection between the components to be connected. In particular, the present invention relates to a method of connecting chip elements to a printed circuit board, and to a pad for such a connection.
2. Description of the Background Art
The cost at the so-called back-end of line (BEOL) in chip production for housing the chips may be reduced by a factor of 10 per chip if the chip is bonded directly onto the printed circuit board or onto the board.
The disadvantage of this direct application of the chips to a printed circuit board exists in the differing expansion coefficients of the materials used, that is in a lack of adjustment of the expansion coefficients (CTE mismatch; CTE=coefficient of temperature expansion). Adhesion problems due to shearing forces occur in the temperature range between −65° C. and +150° C.
The manufacturing processes just described are also referred to as “wafer level package” or “wafer scale assembly”. The important, cost-saving step in the production is achieved by replacing the serial process of housing chips that have already been diced by a parallel process to be carried out on the complete wafer, in which suitable connection elements for providing contact to the circuit board (PCB=printed circuit board) are used. Various connecting techniques have been known by means of which the interfering adhesion problems which occur in the above-mentioned temperature range from −65° C. to +150° C. and are due to the occurring shearing forces are to be avoided. The most current techniques will be briefly explained below.
In accordance with a first technique, the pads of the chip (chip contacts) on the wafer are covered with solder droplets which establish a rigid contact with the printed circuit board by means of a heating step, as is used, for example, in flip-chip technology.
With an increase in the chip size, however, the above-mentioned shearing forces make themselves felt increasingly. A known concept for avoiding the occurring shearing forces due to the thermal mismatch is to provide an elastic dielectric layer arranged between the chip and the board, electrical contact being made via one or several conductors vapor-deposited onto the flexible dielectric.
This approach, however, is disadvantageous in that, in addition, the dielectric layer is to be provided which further must be provided with the corresponding contacting for connecting the pads on the chip and on the board, which entails increased outlay and cost.